【中文摘要】西北工业大学仿生系统芯片交叉研究中心论文TSCA于2026年9月16日被IEEE TVLSI录用为Regular Paper。第一作者为博士生Musheer Abdullah，通讯作者为高武教授。针对脉冲CNN边缘推理各阶段负载差异大、传统同构加速器存在冗余计算和膜状态存储开销高等问题，TSCA采用三元/8位/二值异构多精度架构，包含TCE、STCE和DBC三个专用引擎，并集成5-bit QIF神经元，使膜状态存储降低达75%，精度损失小于0.7个百分点。该处理器在Xilinx Zynq UltraScale+ FPGA上以250 MHz运行，峰值吞吐5.68 TOP/s，MNIST/CIFAR-10/CIFAR-100能效分别为1498/629.8/281.4 FPS/W，且不使用DSP。成果表明，精度感知的架构专门化可有效平衡资源、功耗与性能，面向端到端神经形态边缘推理与近传感智能视觉
Lab News — A paper titled “TSCA: A Heterogeneous Multi-Precision Spiking CNN Processor with Low-Bit Neuron Dynamics for Edge Inference,” has been accepted as a Regular Paper in IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), on Sept. 16th , 2026. The first author of the paper is PhD student Musheer Abdullah, and the corresponding author is Prof. Wu Gao. All authors are with the Interdisciplinary Research Center for Bio-inspired System-on-Chip, Northwestern Polytechnical University.
Fig.1 TSCA replaces conventional homogeneous SCNN processing with a stage-specialized TCE-STCE-DBC pipeline and inter-layer parallelism.
Why spiking CNNs need a smarter chip
Spiking neural networks are attractive for edge AI because they use sparse binary spikes—like the brain. But a full spiking CNN pipeline has very different jobs: input encoding, deep feature extraction, and classification.
Conventional accelerators often handle these stages with a similar architecture, causing redundant temporal computation, unnecessary neuron updates, and high membrane-state storage overhead.
TSCA takes a different approach: give each stage the precision and hardware it needs.
Three engines, three jobs
TSCA combines ternary, 8-bit, and binary computation with low-bit neuron dynamics. Its three specialized engines are:
Ternary Convolution Encoder (TCE): handles the first convolution directly on input pixels using ternary weights and generates spikes in one pass.
Spatiotemporal Computing Engine (STCE): accelerates deeper SCNN layers with high parallelism across channels, kernels, and 2D spatial neurons, integrating a 5-bit Quantized Integrate-and-Fire (QIF) neuron model.
Dual-Binary Classifier (DBC): performs on-processor classification using binary spikes and binary weights, with adaptive average pooling fused into synaptic computation.
These stages are connected through a reconfigurable data-flow orchestrator and executed in a pipelined manner.
The clever trick: 5-bit neurons
A key contribution is the low-bit QIF neuron. Compared with full-precision integrate-and-fire neurons, the 5-bit representation reduces membrane-state storage by up to 75% while adding less than 0.7 percentage points of accuracy loss.
In simple terms: the neuron’s short-term memory is compressed dramatically, but the network still remembers enough to get the answer right.
Fig.2 Proposed low-bit QIF neuron dynamics and representative full-precision versus quantized membrane-potential distributions.
Performance overview
Implemented on a Xilinx Zynq UltraScale+ FPGA at 250 MHz:
Peak throughput: 5.68 TOP/s
Energy efficiency: 1498 FPS/W on MNIST, 629.8 on CIFAR-10, 281.4 on CIFAR-100
DSP blocks used: none
Using no DSP blocks matters for embedded platforms, where dedicated arithmetic resources can limit scalability.
Fig.3 TSCA implementation results: FPGA resource utilization, module-level resource contribution, and power breakdown.
Why it matters
TSCA shows that precision-aware architectural specialization can balance resources, power, and performance for end-to-end neuromorphic edge inference. It also points toward future near- and in-sensor intelligent vision systems—where computation moves closer to the sensor and efficiency is designed in from the start.
